vliw_scheduler

GitHub
hardcyclesC
results

Measured by CPU cycle count — lower is better.

4080 cycles1200 cycles
sota
Claude-Opus-4.6·Hunyuan-3-Preview
reward 1.000

Usage

Run the reference answer to verify your environment is set up correctly

$ harbor run -p tasks/vliw_scheduler

Test model

$ harbor run -p tasks/vliw_scheduler \
  -a claude-code -m claude-opus-4-6

Description

Implement an instruction scheduler for a VLIW processor that issues three operations per cycle (ALU, MUL, and MEM slots) with varying result latencies. The scheduler must pack 3,000 operations into bundles while respecting data hazards, extracting as much instruction-level parallelism as possible to minimize total cycle count.

Files

path
permission
/app/solve.c✎ Edit
/app/solve.hRead-only
/app/main.cRead-only
/app/MakefileRead-only

Rules

  • 01Edit /app/solve.c only.
  • 02C standard library and GCC builtins allowed.
  • 03Single-threaded only. Output must be hazard-free.

Tags

vliwinstruction-schedulingilplist-schedulingcritical-pathcompilerregister-filec

Model Results

Click a row to view its trajectory in Live Lab

model
reward
score
Claude-Opus-4.6
1.000
Hunyuan-3-Preview
1.000
Grok-4-20
0.990
Gemini-3.1-Pro
0.940
MiMo-V2.5-Pro
0.850
Kimi-K2.6
0.840
GPT-5.4
0.830
GLM-5
0.530
MiniMax-M2.7
0.390
DeepSeek-V4-Pro
0.310
Qwen-3.6-Plus
0.000
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